(1) Field of the Invention
The invention relates to the field of semiconductor wafer manufacturing, and more specifically to a method to reduce the size of the scribe lines within the surface of a wafer.
(2) Description of Prior Art
Since the development of integrated circuit technology, semiconductor chips have been made from wafers of semiconductor material whereby each chip contains a plurality of integrated circuits. After the wafer is completed, the individual chip is typically separated from other chips by dicing the wafer into small chips. Thereafter, the individual chips are mounted on carriers of various types, interconnected by wires and further packaged.
The scribe line is used to scribe and break the semiconductor wafer into individual dies. In a typical semiconductor manufacturing process, a plurality of trenches are formed in the surface of each semiconductor wafer by scribing the surface of the semiconductor wafer. Scribing breaks the semiconductor wafer into a plurality of separate die. However, current practice asks for a die width of approximately 150 um. and requires a relatively large portion of the semiconductor surface to apply scribe lines. Current technology results in high losses, thereby reducing chip yield as a result of uneven scribing which causes cracks to form and which extend into the individual die.
The technique of laser scribing is an improvement in that no cracks are formed. However, due to non-uniformity in the planarization of the wafer surface and since the depth of focus of a wafer is difficult to control, unequal breaking of the wafer occurs also reducing the yield of wafers. Laser scribing further requires expensive equipment and adds considerably to the overall semiconductor chip manufacturing cost.
Prior Art has used a silicon etch to perform die separation. It has in the past however proven difficult to produce a photoresist that will stand up against the very strong acids that are used to etch silicon. Another technique uses diamond cutting to scribe the wafer surface. However, the diamond-cutting knife has a relatively large width, typically 50 um., while diamond cutting introduces problems of cutting tolerances. These tolerance problems require that a line width of a minimum of 75 um. is assigned to each line that must be scribed in the wafer surface. It is clear that this process requires the allocation of a relatively large area of the wafer surface that will be used up by the scribing operation.
One of the aspects of chip separation is the uniformity and lack of abrasion of the edges of the chip after the wafer has been separated into individual chips. This aspect becomes even more critical in a chip packaging environment where chips are stacked in multiple layers, the layers being separated by inter-level dielectrics. Increasing chip packaging density and the number of layers created to accomplish this density results in chips being in very close physical proximity to other parts of the complete chip package, most notably inter-level metal connects and metal interconnecting networks. This stacking of chips in increasing chip density results in problems caused by uneven separation of the chips from the wafer (the edge of the chip is not smooth and can therefore penetrate surrounding layers) or by affecting the thickness of layers that have been created in the chip. For instance thick layers of passivation where a heavy layer of polyimide is used as a passivation layer. Thin film processing is required to interconnect the chips after they have been separated from the wafer. Any of the defects mentioned have a negative impact on this thin film processing resulting in loss of chip yield. Improper chip separation from the wafer also limits the size of the stack that can be created using these chips. Current technology uses sawing or laser cutting to separate the chips, chip dicing defects can for these methods be controlled by controlling the speed by which the wafer is diced. This approach has however met with only limited success since, for most operations of this type, the dicing speed must be reduced resulting in reduced chip throughput while a time consuming post-dicing inspection must still be performed to verify chip edge characteristics.
Of further importance in dicing chips is the uniformity with which chips are diced since this uniformity affects the accuracy with which the chips can be mounted in a multi-stack chip configuration. Chip dicing operations must therefore result in chips of uniform dimensions, many of the chip mounting and packaging operations are performed using high speed and highly accurate machinery where tight tolerances and tolerance control is of extreme importance. Operations are performed on chips after they have been mounted in a multi-chip package such as the formation of interconnecting metal vias or the deposition of matching metal networks. These operations further highlight the need for consistent chip dicing operations under closed control of chip parameters. Any misalignment during the formation of the operations of chip interconnect results in expensive and time consuming rework whereby this rework can in many cases be performed only a limited number of times before the entire package must be scrapped.
In dicing chips, it is important that the dicing operation does not introduce variations in the thickness of the deposited surface layers within the chip. No foreign material of any kind can therefore be introduced (during the process of dicing) that remains on the chip after the chip has been diced. If dicing is performed using etchants, these etchants for the same reason can not exhibit chemical reactions with any of the surfaces with which the etchants come into contact. Such a chemical reaction can, for instance, affect the thickness of deposited passivation layers further taking away from the quality of the chip.
In a typical semiconductor manufacturing process, the substrate is, after the process of formation of the individual devices or components in the surface of the substrate has been completed, separated into its separate components. For this purpose, a plurality of trenches is formed in the surface of the substrate, these trenches can form separate transistor cells or capacitor cells or individual chips. Trenches that are created on the surface of the substrate take up valuable substrate surface area. It is therefore important to accomplish the separation of the individual components of a substrate in a manner such that the quality of this component is not affected while the surface area of the substrate that must be sacrificed to gain the individual components must be kept to a minimum. Dependent on the thickness of the wafer, the trenches that are created in the surface of the wafer may have to penetrate the wafer further. The trench is formed by etching, current processes frequently require added technology that validates the depth of the trench at the end of the etch process. This determines whether the substrate that has been etched is adequately etched and can therefore be separated in its individual components. A typical method of determining the end of the trench-formation process is the use of light reflecting apparatus of considerable complexity and therefore considerable expense. A method where the parameters of trench width and depth can be controlled or adequately predicted based on the processing parameters that are used for the formation of the trench is therefore to be preferred. The trench must have a desired and well-defined profile whereby it must be possible to create such a trench uniformly, consistently and at a reasonable cost. Trench depth is thereby important since the deeper the trench, the easier will be the step of actually separating the chips and other substrate components.
Reduction on scribe line width will result in the availability of a larger percentage of the wafer surface that can be dedicated to the creation of integrated circuits. The present invention addresses this aspect of semiconductor chip manufacturing.
U.S. Pat. No. 4,096,619 (Cook, Jr.) shows a process of etching trenches (by anodizing) in a scribe area and breaking the wafer by stress (not dicing). See abstract; see Cols. 2 and 3. This patent is close to the invention.
U.S. Pat. No. 5,614,445 (Hirabayashi) discloses a process where trench grooves are formed in the integrated circuit region of the wafer and dummy etched grooves are formed in a scribe line zone of the wafer. Both the trench grooves and the dummy etched grooves are filled with polycrystalline silicon to provide a smooth wafer surface. The wafer is then cleaved along the scribe line zone. Note that the patent generally claims "separating said semiconductor wafer into individual chips" and may not be limited to Dicing.
U.S. Pat. No. 5,023,188 (Tanaka) discloses a method to measure trench depths.
U.S. Pat. No. 5,691,248 (Cronin et al.) discloses a method to dice/separate wafers by forming trenches in the kerf.